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low cost, low power, true rms - to - dc converter data sheet ad8436 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2011 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features delivers true rms or average rectified value of ac waveform fast settling at all input levels accuracy: 10 v 0. 2 5% of reading (b grade) wide dynamic input range 100 v rms to 3 v rms (8.5 v p - p) full - scale input range l arger inputs with external scaling wide bandwidth: 1 mh z for ?3 db (300 mv) 65 khz for additional 1% error zero converter dc output offset no residual switching products specified at 300 mv rms input accurate conversion with crest factors up to 10 low power: 300 a typical at 2.4 v high - z fet separately powered input buffer r in 10 12 , c in 2 pf precision dc output buffer wide power supply voltage range dual: 2. 4 v to 1 8 v ; s ingle: 4.8 v to 36 v 4 mm 4 mm lf csp and 8 mm 6 mm qsop packages esd p rotected functional block dia gram vee cavg vcc ignd out ibufgn rms ibufout ibufin+ sum 8k? 100k? 16k? 100k? ognd 10k? 10k? fet op amp 10pf ibufin? obufout obufin+ obufin? 16k? dc buffer ad8436 ? + rms core ? + ccf 10033-001 figure 1. general description the ad8436 is a new generation, translinear precision, low power, true rms - to - dc converter loaded with options. it computes a precise dc equivalent of the rms value of ac wave - forms, including complex patterns such as those generated by switch mode power supplies and t riacs . its accuracy spans a wide range of input levels ( see figure 2 ) and temperatures. t he e nsured accuracy of 0. 5% and 10 v output offset result from the latest analog devices, inc., t echnology . the c rest factor error is <0.5% for cf values between 1 and 10. the ad8436 delivers true rms results at l ess cost than misleading peak, averaging , or digital solutions. there is no programming expense or process or overhead to consider , and the 4 mm 4 mm packag e easily fits into tight applications. on - board buffer amplifiers enable the widest ra nge of options for any rms - to - dc converter available, regardless of cost. for minimal applications, only a single external averaging capacitor is required . the b uilt - in high impedance fet buffer provide s an interfac e for external attenuators, frequency compensation , or driving low impedance loads. a matched pair of internal resistors enables an easily configurable gain - of - two or more , extending the us able input range even lower. the low power , precision input buffer m akes the ad8436 attractive for use in portable multi - meters and other battery - powered applicati ons. the precision dc output buffer minimizes errors when driving low impedance loads with extremely low offset volt ages , thanks to internal bias current cancellation. unlike digital solutions, the ad8436 has no switching c ircuitry limit ing performance at high or low amplitudes (see figure 2 ). a u s able response of < 100 v and > 3 v extends the dynamic range with no external s caling, accommodating demanding low level signal conditions and allowing ample over range withou t clipping . 1mv 10mv 1v 100mv ad8436 greater input dynamic range 100v 3v ? solution 10033-002 figure 2 . usable dynamic range of the ad8436 vs. ? the ad8436 operates from single or dual supplies of 2.4 v (4.8 v) to 18 v (36 v). a and j grades are available in a compact 4 mm 4 mm , 20- lead chip - scale package ; a and b grade s are available in a 20 - lead qsop package . the operating temperature range s are ?40c to 125c for a and b grade s and 0c to 70c for j grade .
ad8436 data sheet rev. b | page 2 of 24 t able of c ontents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specificatio ns ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 test circuits ........................................................................................9 theory of operation ...................................................................... 10 overview ..................................................................................... 10 applications information .............................................................. 12 using the ad8436 ....................................................................... 12 ad8436 evaluation board ............................................................. 17 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 21 revision history 1/13 rev. a to rev. b added b grade throughout ............................................. universal changes to figure 1 and c hanges to general description .......... 1 changes to table 1 ............................................................................ 3 changes to figure 3 ......................................................................... 5 changes to figure 9 and figure 10 ................................................. 6 changes to fet input buffer sect ion .......................................... 11 changes to averaging capacitor considerations rms accuracy section and changes to figure 28 ................................ 12 deleted capacitor construction section; a dded c avg capacitor styles section ................................................................. 13 added converting to average rectified value section ............. 15 changes to figure 41 ...................................................................... 16 changes to evaluation board section .......................................... 17 changes to figure 48 ...................................................................... 19 changes to outline dimensions ................................................... 20 changes t o ordering guide .......................................................... 21 7 /12 rev. 0 to rev. a added 20- lead qsop ........................................................ universal changes to features section and general d escription section . 1 changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 4 changes to table 3 and a dded figure 4 and added table 4; renumbered sequentially ................................................................ 5 changes to equation 1 and change to column one heading in table 5 .......................................................................................... 10 changes to averaging capacitor considerat ions rms accuracy and to post conversion ripple reduction filter and changes to figure 27 caption ................................................ 12 changes to figure 30 to figure 32 ................................................ 13 changes to using the fet input buffer section and using the output buffer section .................................................................... 14 changes to figure 38 and figure 41 and added converting to rectified average value section .............................................. 15 chan ges to figure 41 ...................................................................... 16 changes to figure 42 to figure 46 ................................................ 17 chang es to figure 47 and figure 48 ............................................ 18 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 7/11 revision 0: initial version
data sheet ad8436 rev. b | page 3 of 24 specifications e in = 300 mv (rms) , frequency = 1 khz sin usoidal, ac - coupled, v s = 5 v , t a = 25c, c av g = 10 f, unless otherwise specified. table 1 . ad8436a, ad8436j ad8436b parameter conditions min typ max min typ max units rms core conversion error default conditions 10 ? 0.5 0 0 10 + 0.5 10 ? 0.25 0 0 10 + 0.25 v /% rdg vs. temperature ?40c < t < 125 c 0.006 0.006 %/c vs. rail voltage 2.4 v to 18 v 0.013 0.013 %/v input v os dc - coupled ?500 0 +500 ?250 0 + 250 v output v os ac - coupled input 0 0 v vs. temperature ?40 c < t < 125c 0.3 0.3 v/c dc reversal error dc - coupled, v in = 300 mv ?1.5 0 +1.5 ?1.0 0 + 1.0 % nonlinearity e in = 2 mv to 500 mv ac 0.2 0.2 % crest factor error (additional) 1 < cf < 10 ccf = 0.1 f ?0.5 +0.5 ?0.5 +0.5 % peak input voltage ?v s ? 0.7 +v s + 0.7 ?v s ? 0.7 +v s + 0.7 v input resistance 7.92 8 8.08 7.92 8 8.08 k? response v in = 300 mv rms 1% error (additional) 65 65 khz 3 db bandwidth 1 1 mhz settling time 0.1% rising/falling 148/341 148/341 ms 0.01% rising/falling 158/350 158/350 ms output resistance 15.68 16 16.32 15.68 16 16.32 k? supply current no input 325 365 325 365 a input buffer voltage swing g = 1 input ac - or dc - coupled ?v s +v s ?v s +v s v output ac - coupled to pin rms ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 mv offset voltage ?1 0 +1 ? 0.5 0 + 0.5 mv input bias current 50 50 pa input resistance 10 12 10 12 ? response (frequency) 0.1 db 950 950 khz 3 db bandwidth 2.1 2.1 mhz supply current 100 160 200 100 160 200 a optional gain resistor ?9.9 +10 +10.1 ?9.9 +10 +10.1 k? gain error g = 1 0.05 0.05 % output buffer r l = offset voltage connected to pin out ?200 0 +200 ?15 0 0 + 150 v input current (i b ) 2 5 1 2 5 1 na output swing (voltage) ?v s + 50e - 6 +v s ? 1 ?v s + 50e - 6 +v s ? 1 v output drive current ?0.5 (sink) +15 (source) ?0.5 (sink) +15 (source) ma gain error 0.003 0.01 0.003 0.01 % supply current 40 70 40 70 a supply voltage dual 2.4 18 2.4 18 v single 4.8 36 4.8 36 v 1 i b max measured at power up. settles to typical value in <15 seconds.
ad8436 data sheet rev. b | page 4 of 24 absolute maximum rat ings table 2 . parameter rating voltage supply 18 v input v s differential input +v s and ?v s power dissipation cp -20- 10 lfcsp without thermal pad 1.2 w cp -20- 10 lfcsp with thermal pad 2.1 w rq package 1.1 w output short - circuit duration indefinite temperature operating range ?40c to +125c storage range ?65c to +125c lead soldering (60 sec) 300c ja cp -20- 10 lfcsp without thermal pad 86c/w cp -20- 10 lfcsp with thermal pad 48c/w rq - 20 package 95c/w esd rating 2 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. j a is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. esd caution
data sheet ad8436 rev. b | page 5 of 24 pin configuration and function descrip tions 16 20 15 10 6 ad8436 top view (not to scale) 11 pin 1 indicator vee cavg vcc obufout ignd obufin+ obufin? obufv+ out dnc notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed pad connection is optional. ibufgn dnc ibufout ibufin+ sum ibufv + rms ccf ognd ibufin? 1 5 10033-003 figure 3 . pin configuration, top view, cp - 20 - 10 table 3 . pin function descriptions , cp - 20 - 10 pin o. nemonic description 1 dnc do not connect. used for factory test. 2 rms ac input to the rms c ore. 3 ibuf out fet input b uffer output pin . 4 ibufin C fet i nput b uffer inverting i nput pin . 5 ibufin + fet input buffer noninverting input pin . 6 ibufgn optional 10 k? precision gain resistor. 7 dnc do not connect. used for factory test. 8 ognd i nternal 16 k ? i -to - v r esistor . 9 out rms c ore voltage or c urrent output . 10 vee negative s upply rail. 11 ignd half supply node . 12 obufin+ o utput b uffer noninverting i nput pin . 13 obufin ? o utput b uffer inverting i nput pin . 14 obufout o utput b uffer o utput pin . 15 obufv+ p ower p in for the o utput b uffer . 16 ibufv+ p ower p in for the i nput b uffer. 17 vcc positive supply rail for the rms c ore. 18 ccf connection for crest factor capacitor. 19 cavg connection for a veraging c apacitor. 20 sum summing amplifier input pin . ep dnc exposed pad connection to ground pad optional . notes 1. dnc = do not connect. do not connect to this pin. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 dnc rms ibufout ibufgn ibufin+ ibufin? sum ccf vcc ibufv+ obufin? obufout obufv+ out ognd dnc vee ignd obufin+ cavg top view (not to scale) ad8436 10033-104 figure 4 . pin configuration, rq - 20 table 4 . pin function descriptions, rq - 20 pin o. nemonic description 1 sum summing amplifier input pin . 2 dnc do not connect. used for factory test. 3 rms ac input to the rms core. 4 ibufout fet input buffer output pin . 5 ibufin C fet input buffer inverting input pin . 6 ibufin+ fet input buffer noninverting input pin . 7 ibufgn optional 10 k? precision gain resistor. 8 dnc do not connect. used for factory test. 9 ognd internal 16 k ? i -to - v resistor . 10 out rms core voltage or current output . 11 vee negative supply rail. 12 ignd half supply node . 13 obufin+ output buffer noninverting input pin . 14 obufin? output buffer inverting input pin . 15 obufout output buffer output pin . 16 obufv+ power pin for the output buffer. 17 ibufv+ power pin for the input buffer. 18 vcc positive supply rail for the rms core. 19 ccf connection for crest factor capacitor. 20 cavg connection for averaging capacitor.
ad8436 data sheet rev. b | page 6 of 24 typical performance characteristics t a = 25c, v s = 5 v , c av g = 10 f , 1 khz sine wave , unless otherwise indicate d. input level (v rms) 1v 100 1k frequency (hz) 100k 10k 10mv 5v 100v 100mv 1mv 5m 1m 50 50v ?3db bw 10033-004 figure 5. rms core frequency response (s ee figure 21 ) ?3db bw v s = 2.4v 10033-005 1v 100 1k frequency (hz) 100k 10k 10mv 5v 100v 100mv 1mv 5m 1m 50 50v input level (v rms) figure 6. rms core frequency response with v s = 2.4 v ( see figure 21 ) ?3db bw v s = 15v 10033-006 input level (v rms) 1v 100 1k frequency (hz) 100k 10k 10mv 5v 100v 100mv 1mv 5m 1m 50 50v figure 7. rms core frequency response with v s = 15 v ( see figure 21 ) ?3db bw v s = 4.8v 10033-007 input level (v rms) 1v 100 1k frequency (hz) 100k 10k 10mv 5v 100v 100mv 1mv 5m 1m 50 50v figure 8. rms core frequency response with v s = +4.8 v ( see figure 22 ) gain (db) 12 100 1k frequency (hz) 100k 10k 0 15 3 9 6 5m 1m ?15 ?12 ?3 ?9 ?6 e in = 3.5mv rms 10033-008 gain = 6db gain = 0db figure 9 . input buffer , small signal bandwidth at 0 db and 6 db gain gain (db) 12 100 1k frequency (hz) 100k 10k 0 15 3 9 6 5m 1m ?15 ?12 ?3 ?9 ?6 e in = 300mv rms 10033-009 gain = 6db gain = 0db figure 10 . input buffer , l arge signal bandwidth at 0 db and 6 db ga in
data sheet ad8436 rev. b | page 7 of 24 gain (db) 12 100 1k frequency (hz) 100k 10k 0 15 3 9 6 5m 1m ?15 ?12 ?3 ?9 ?6 e in = 3.5mv rms 10033-010 figure 11 . output buffer , small s ignal bandwidth 20 supply voltage (v) 8 4 2 6 14 12 10 0.3 0.5 0.4 0 ?0.1 cavg = 10f 8 samples normalized error (%) 0 ?0.3 ?0.4 ?0.2 0.2 0.1 ?0.5 18 16 10033-0 1 1 figure 12 . additional error vs. supply voltage input level (v rms) 4 6 supply voltage (v) 10 8 0.8 2.0 1.2 0.4 14 12 2 0 16 18 0 1.6 10033-012 figure 13 . core input voltage for 1% error vs. supply voltage additional error (% of reading) crest factor ratio 2 0 5 6 4 0 8 10 10 ?5 ?10 cavg = 10f cavg = 10f ccf = 0.1f p w = 100s 10033-013 figure 14 . crest factor e rror vs. c rest factor for c avg and c avg and c cf capacitor combinations additional error (% of reading) temperature (c) 25 0 0.50 0.25 0.75 75 50 0 100 125 1.00 ?25 ?50 ?0.50 ?0.25 ?0.75 ?1.00 10033-014 figure 15 . additional conversion error vs. temperature supply current (ma) 2.5 0.5 1.0 input voltage (v rms) 2.0 1.5 1.5 0.5 2.0 1.0 0 0 v s = 2.4v v s = 15v v s = 5v 10033-015 figure 16 . rms core supply current vs. input for v s = 2.4 v, 5 v , and 15 v
ad8436 data sheet rev. b | page 8 of 24 bias current (pa) temperature (c) 25 0 70 60 80 75 50 0 100 125 90 ?25 ?50 40 50 30 20 10 ?10 10033-016 figure 17 . fet input buffer bias current vs . temperature input offset voltage (v) temperature (c) 25 0 500 250 750 75 50 0 100 125 1000 ?500 ?250 ?750 ?1000 ?25 ?50 10033-018 figure 18 . input offset v oltage of fet buffer vs . temperature input offset voltage (v) temperature (c) 25 0 100 250 150 50 75 50 0 100 125 200 ?100 ?250 ?150 ?50 ?200 ?25 ?50 10033-019 figure 19 . output buffer v os vs. temperature 1khz 300mv rms burst input time (50ms/div) 1khz 1mv rms burst input 300mv dc out 1mv dc out cavg = 10f 0v 0v 0v 0v 10033-020 figure 20 . transition times with 1 khz b urst at two input levels (see theory of operation section)
data sheet ad8436 rev. b | page 9 of 24 test circuits precision dmm signal source out rms + 5 v 10f ac-in monitor precision dmm 4 . 7f vee cav vcc 100k? 100k? 16k? ognd ?5v ignd rms core 10033-021 figure 21 . core response test circuit using dual supplies precision dmm signal source out rms 4.80v 10f ac-in monitor precision dmm 4.7f 4.7f vee cav vcc 100k? 100k? 16k? ognd ignd rms core 10033-022 figure 22 . core response test circuit using a single supply function generator precision dmm out rms + 5 v 10f ac-in monitor precision dmm 4 . 7f vee cav vcc 100k? 100k? 16k? ognd ?5v ignd rms core 10033-023 figure 23 . crest factor test circuit
ad8436 data sheet rev. b | page 10 of 24 theory of operation overview the ad8436 is an implicit function rms - to - dc converter that renders a dc voltage dependent on the rms (heating value) of an ac voltage. in addition to the basic converter, this highly integrated functional circuit block includes two fully independent , optional amplifiers, a standalone fet input buffer amplifier and a precision dc output buffer amplifier (see figure 1 ). the rms core includes a precision current responding ful l - wave rectifier and a log - anti log transistor array for current squaring and square rooting to imple - ment the cl assic expression for rms (see e quation 1). for basic applications, the converter requires only an external capacitor, for averaging (see figure 31 ). the optional on - board amplifiers offer utility and flexibility in a variety of applications without incurring additional circuit board footprint. for lowest power, the amplifier supply pins are left unconnected. why rms ? the rms value of an ac voltage waveform is equal to the dc voltage providi ng the same heating power to a load. a common measure - ment technique for ac waveforms is to rectify the signal in a straightforward way using a diode array of some sort, resulting in the average value. the average value of various waveforms (sine, square, and triangular, for example ) varies widely; true rms is the only metric that achieves equivalency for all ac waveforms. see table 5 for non - rms - responding circuit er rors. the acronym rms means root - mean - square and reads as follows: the square root of the average of the sum of the squares of the peak values of any waveform. rms is shown in the following equation: 1 t e rms = v(t) 2 dt 0 t (1) for additional information , select s ection i of the 2 nd ed ition of the analog devices rms - to - dc applications guide . rms core the core consists of a voltage - to - current converter (precision resistor), absolute value , a nd trans linear sections. the trans linear section exploits the properties of the bipolar transistor junctions for squaring and root extraction (see figure 24) . the ext ernal capacitor (cavg) provides for averaging the product. figure 20 shows that there is no effect of signal input on the transition times, as seen in the dc output. although the rms core responds to input voltages, the conversion process is current sensitive. if the rms input is ac - coupled, as recomme nded, there is no output offset voltage, as reflected in table 1 . if the rms input is dc - coupled, the input offset voltage i s reflected in the output and can be calibrated as with any fixed error. v? a c in v+ out + ? v + 5k cavg absolute value circuit v-t o-i 16k 10033-024 figure 24 . rms core block diagram table 5 . general ac parameters waveform t ype ( 1 v peak ) crest factor r ms v alue reading of an average value circuit calibrated to an rms sine w ave error (%) sine 1.414 0.707 0.707 0 square 1.00 1.00 1.11 11.0 triangle 1.73 0 .577 0.555 ?3.8 noise 3 0 .333 0.295 rectangular 2 0.5 0.278 ?11.4 pulse 10 0.1 0.011 ?44 scr ?89 dc = 50% 2 0.495 0.354 ?28 dc = 25% 4.7 0.212 0.150 ?30
data sheet ad8436 rev. b | page 11 of 24 the 16 k resistor in the output converts the output current to a dc voltage that can be connected to the output buffer or to the circuit that follows . the output appears as a voltage source in series with 16 k. if a current output is desired, the resistor connection to ground is l eft open and the output current is applied to a subsequent circuit , such as the summing node of a current summing amplifier. thus, the core has both current and voltage outputs, depending on the configuration. for a voltage output with 0 source impedance, use the output buffer. the offset voltage of the buffer is 25 v or 50 v, depending on th e grade. fet input buffer because the v - to - i input resistor value of the ad8436 rms core is 8 k?, a high input impedance buffer is often used between rms - dc converters and finite impedance sources. the optional jfet input op amp minimi zes attenuation and uncouples common input amenities , such as resistive voltage dividers or resistors used to terminate current tran sformers. the wide bandwidth of the fet bu ffer is well matched to the rms core bandwidth so that no information is lost due to serial band - width effects. although the input buffer consumes little current, the buffer supply is independently accessible and c an be disconnected to reduce power. optional matched 10 k? input and feedback resistors are provided on chip. c onsult the applications information section to learn ho w these resistors can be used. the 3 db bandwidth of the input buffer is 2.7 mhz at 10 mv rms input and approximately 1.5 mhz at 1 v rms. the amplifier gain and bandwidth are sufficient for applications requiring modest ga in or response enhancement to a fe w hundred kilohertz ( khz ), if desired. configurations of the input buffer are discussed in the applications information section . precision output buffer the precision output buffer is a bipolar input amplifier, laser tri mmed to cancel input offset voltage errors. as with the input buffer , the supply current is very low (<50 a , typically), and the power can be disconnected for power savings if the buffer is not needed . be sure that the non inverting input is also disc onnected from the core output ( out) if the buffer supply pin is discon - nected . although the input curre nt of the buffer is very low, a laser - trimmed 16 k resistor , connected in series with the inverting inpu t , offset s any self - bias offset voltage. the output buffer ca n be configured as a single or two - pole low - pass filter using circuits shown in the applications information section. residual output ripple is reduced, without affecting the converted dc output. as the response approaches the low frequency end of the bandwidth, the ripple rises, dependent on the value of the averaging capacitor. figure 27 shows the effects of four combinations of averaging and filter capacitors. although the filter capacitor reduces the ripple for any given frequency, the dc error is unaffected. of cours e, a larger value averaging capacitor can be selected, at a larger cost. the advantage of using a low - pass filter is that a small value of filter capacitor, in conjunction with the 16 k ? output resistor, reduces ripple and permits a smaller averaging capacitor, effecting a cost savings. the recommended capacitor values for operation to 40 hz are 10 f for averaging and 3.3 f for filter. dynamic range the ad8436 is a translinear rms - to - dc converter with exceptional dynamic range. although accuracy varies slightly more at the extreme input values, the device still converts with no spurious noise or dropout. figure 25 is a plot of the rms/dc transfer function near zero voltage. unlike processor or other solutions, residual errors at very low input levels can be disregarded for most applications. output voltage (mv dc) input voltage (mv dc) 30 20 10 0 0 30 20 10 ?10 ?20 ?30 ? or other digital solutions cannot work at zero volts ad8436 solution 10033-025 figure 25 . dc transfer function near z ero
ad8436 data sheet rev. b | page 12 of 24 applications information using the ad8436 this section describes the p ower supply and feature options, as well as the function and selection of averaging and filt er capacitor values . averaging and filtering op tions are shown graphically and appl y to all circuit configurations. averaging capacitor considerations rms a ccuracy typical ad8436 applications require only a single external capaci tor (cavg ) connected to the cavg pin (see figure 31 ). the function of the averaging capacitor is to compute the mean ( that is, average value) of the sum of the squares. averaging (that is, integration) follows the rms core, where the input current is squar ed . the mean value is the average value of the squa red input voltage over several input waveform periods. the rms error is directly affected by the number of periods averaged, as is the resultant peak - to - peak ripple. the result of the conversion process is a dc component and a ripple component whose frequency is twice that of the input. the rms conversion accuracy depends on the value of cavg, so the value selected need only be large enough to average enough periods at the lowest frequency of interest to yield the required rms accuracy. figure 28 is a plot of rms error vs. frequency for various averaging capacitor values. to use figure 28 , simply locate the frequency of interest and acceptable rms error on the horizontal and vertical scales, respectively. then choose or estimate the next highest capacitor value adjacent to where the frequency a nd error lines intersect (for an example, see the orange circle in figure 28). post conversion ripple reduction filter input rectification included in the ad8436 i ntroduces a residual ripple component th at is dependent on the value of c avg and twice the input signal frequency for symmetrical input wave - forms . for sampling applications such as a high resolution adc, the ripple component may cause one or more lsbs to cycle, and low value display numerals to flash . ripple is reduced by increasing the value of the averaging capacitor, or by post conversion filtering. ripple reduction following conversion i s far more efficient because the ripple average value has been converted to its rms value. capacitor values for post - conversion filtering are significantly less than the equivalent averaging capacitor value for the same level of ripple reduction. this appr oach requires only a single capacitor connected to the out pin (see figure 26 ). the capacitor value correlates to the simple frequency relation of ? r - c, where r is fixed at 16 k?. out 16k? ognd core clpf dc output 9 8 10033-026 figure 26 . simple one - pole post conversion filter as seen in figure 27 , cavg alone determines the rms error, and clpf serves purely to reduce ripple. figure 27 shows a constant rms error for clpf values of 0.33 f and 3. 3 f; only the ripple is affected. rms error (%) frequency (hz) 1 0 100 1k ?1 ?2 10 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 cavg = 10f clpf = 0.33f or 3.3f cavg = 1f clpf = 0.33f or 3.3f 10033-027 figure 27 . rms error vs . frequency for two val ues of cavg and clpf (n ote that on ly cavg value affects rms error; clp f has no effect . ) 10033-028 conversion error (%) frequency (hz) ?0.5 ?1.5 0 ?1.0 ?2.0 1k 100 10 2 see text cavg = 0.22f 0.47f 2.2f 4.7f 10f 22f 50f 1f figure 28 . conversion error vs. frequency for various values of cavg
data sheet ad8436 rev. b | page 13 of 24 for simplicity, figure 29 shows ripple vs . frequency for four combinations of cavg and clpf ripple error (v p-p) input frequency (hz) 1 0.0001 100 1k 10 0.001 0.01 0.1 cavg = 1f, clpf = 0.33f cavg = 10f, clpf = 3.3f cavg = 10f, clpf = 0.33f cavg = 1f, clpf = 3.3f ac input = 300mv rms 10033-029 figure 29 . residual ripple v oltage for various filter configurations figure 30 shows the effects of averaging and post - rms filter capacitors on transition and settling times using a 10 - cycle, 50 hz, 1 second period burst signal input to demonstrate time - domain behavior. in this instance , the averaging capacitor value was 10 f , yielding a ripple value of 6 mv rms. a post conversion capacitor (clpf ) of 0 .68 f reduced the ripple to 1 mv rms. an averaging capacitor value of 82 f reduced the ripple to 1 mv but extended the transition time (and cost) significantly. 10033-130 input 50hz 10 cycle burst 400mv/div cavg = 10f for both plots, but red plot has no low-pass filter, green plot has clpf = 0.68f 10mv/div time (100ms/div) cavg = 82f figure 30 . effect s of various filter options on t ransition times cavg capacitor styles when selecting a capa citor style for cavg there are certain tradeoffs. for general usage, such as most dmm or power measurement applications where input amplitudes are typically greater than 1 mv, surface mo unt tantalums are the best over all choice for space, performance , and economy. for input amplitudes less than around a millivolt, low dc leakage capacitors , such as film or x8l mlcs , maintain rms conversion accuracy . metalized polyester or similar film styles are best, as long as the temperature range is appropriate. x8l gr ade mlcs are rated for hi gh temperatures (125c or 150c ) , but are available only up to 10 f. never use electrolytic capacitors, or x7r or lower grade ceramics. basic core connections m any applications require only a single external capacitor for averaging. a 10 f capacito r is more than adequate for acceptable rms error s at line frequencies and below. the signal source sees the input 8 k voltage - to - current conversion resis tor at p in rms; thus , the ideal source impedance is a voltage source (0 s ource impedance). if a non - zero signal source impedance cannot be avoided, be sure to account for any series connected voltage drop. an input coupling capacitor must be used t o realize the near - zero output offset voltage feature o f the ad8436 . select a coupling capacit or value that is appropriate for the lowest expected operating frequency of interest . as a rule of thumb, the input coupling capacitor ca n be the same as or half the value of the averaging capacito r because the time constants are similar. for a 10 f averaging capacitor, a 4.7 f or 10 f tantalum capacitor is a good choice (s ee figure 31) . 10033-131 2 rms 9 out ad8436 11 ignd 19 cavg 10 vee ?5v 8 ognd 17 vcc 4.7f or 10f +* +5v 10f cavg +* *for polarized capacitor styles. figure 31 . basic application s circuit using a capacitor for high crest factor a pplications the ad8436 contains a unique feature to reduce large crest factor errors . crest factor is often overlooked when considering the requirements of rms - to - dc converters, but it is very important when working with signals with spikes or high peaks. the crest factor is de fined as the ratio of peak voltage to rms. see table 5 for crest factors for some common waveforms. 10033-132 2 rms 9 out ad8436 11 ignd 19 cavg 18 ccf 10 vee ?5v 8 ognd 17 vcc 4.7f or 10f +* +5v 10f cavg +* 0.1f ccf *for polarized capacitor styles. figure 32 . connection f or additional crest factor performance crest factor performance is mostly applicable for unexpected waveforms such as switching transients in switch mode power supplies. in such applications, most of the energy is in these peaks and can be destructive to the circuitry involved , although the average ac value can be quite low.
ad8436 data sheet rev. b | page 14 of 24 figure 14 shows the effects of an additional crest factor capacitor of 0.1 f and an averaging capacitor of 10 f. t h e larger capacitor serves to average the energy over long spaces between pulses, while the ccf capacitor charges and holds the energy within the relatively narrow pulse. using the fet input b uffer the on - chip fet input buffer is an uncommitted fet input op amp used for driving the 8 k? i - to - v input resist or of the rms core. pin ibufout, pin ibufin? , and pin ibufin+ are the i/o , pin ibufingn is an optional connection for gain in the input buffer , and p in ibuf v+ connects power to the buffer . connecting p in ibufv+ to the positive rail is the only pow er connection required because the negative rail is internally connected. because the input stage is a fet and the input impedance must be very high to p re vent loading of the source, a large value (10 m?) resistor is connected from midsupply at p in ignd to p in ibufin+ to prevent the input gate from floating high. for unity gain, connect the ibufout pin to the ibufin? pin . for a gain of 2 , connect the ibufgn pin to ground. see figure 9 and figure 10 for large and small signal responses at the two built - in gain options. the offset voltage of the input buffer is 500 v, depending on grade. a c apacitor connected between the buffer output pin (ibufout) and the rms pin is recommende d so that the input buffer offset voltage does no t contribute to the overall error. select the capacitor value for least minimum error at the lowest operating frequency. figure 3 3 is a schematic showing internal compo nents and pin connections. ibufout ibufin+ ibufin? ? + ibufgn 10k? 10k? 10pf 6 5 4 3 2 rms 10f 0.47f 10m? 11 ignd 16 ibufv+ 10033-033 figure 33 . connecting the fet input buffer capacitor coupling at the input and output of the fet buffer is recommended to avoid transferring the buffer offset voltage to the output. although the fet input impedance is extremely high, the 10 m centering resistor connected to ignd must be taken into account when selecting an input capacitor value. this is simply an impedance calculation using the lowest desired frequency, and finding a capacitor value based on the least attenuation desired. because the 10 k resistors are c losely matched and trimmed to a high tolerance, the i nput buffer gain can be increased to several hundred with an external resistor connected to p in ibufin? . the bandwidth diminishe s at the typical rate of a decade per 20 db of gain, and the output voltage range is constrained. the small signal response , shown in figure 9 , serves as a guide. for example, suppose one wanted to detect small input signals at power line frequencies? an external 10 ? resistor connected from ibufin? to ground sets the gain to 101 an d the 3 db bandwidth to ~ 30 khz, which is more than adequate for amplifying power line frequencies. using the output b uffer the ad8436 output buffer is a precision op amp optimized for high dc accuracy . figure 34 shows a block diagram of the basic amplifier and i/o pins. th e amplifier is often configured as a unity gain follower but is easily configured for gain, as a sallen - key low - pass filter (in co njunction with the built - in 16 k i - to - v resistor ) . note that an additional 16 k? on - chip precision resistor in series with the inverting input of the amplifier bala nce s output offset voltages resulting from the bias current from the non inverting amplifier . the output buffer is disconnec ted from p in out for precision core measurements. as with the input fet buffer, the amplifier positive supply is disconnected when not needed . i n normal circumstances, the buffers ar e connected to the same supply as the core. figure 35 shows the signal connections to the output buffer . note that the input offset voltage contributi on by the bias currents are balanced by equal value series resistors, resulting in near zero offset voltage . obufout obufin+ obufin? 16k? output buffer ? + 10033-034 figure 34 . output buffer block diagram out 16k? 16k? ognd obufout obufin+ obufin? ? + core ibias 9 8 ibias 14 13 12 10033-035 figure 35 . basic output buffer connections for applications requiring ripple suppre ssion in addition to the single - pole output filter described previously , the output buffer is configurable as a two - pole sallen - key filter using two external resistors and two capacitors. at just over 100 khz, the amplif ier has enough bandwidth to function as an active filter for low frequencies such as power line ripple. for a modest savings in cost and complexity, the external 16 k feedback resistor can be omitted , resulting in slightly higher v os (80 v).
data sheet ad8436 rev. b | page 15 of 24 16k? 16k? 16k? 16k? ognd obufout obufin + obufin ? ? + core c 8 14 13 12 9 out 10033-036 2c figure 36 . output bu ffer amplifier configured as a two - pole, sallen - key low - pass f ilter configure the output buffer (see figure 37) to invert dc output. out 16k? 16k? ognd obufout obufin+ obufin? core 32.4k? 8 14 12 13 9 ? + 10033-037 figure 37 . inverting output c onfiguration current output option if a cur rent output is required, conne ct the current output, out, to the desti nation load. to maximize precision, provide a means for external calibration to replace the interna l trimmed resistor, which is by passed. this configuration is useful for conve - nient summing of the ad8436 result with another voltage, or for polarity inversion. ? + 8k? 15k? 16k? 19 cavg 18 ccf 9 out 2 rms 8 ognd direction of dc output current 2k? (optional) inverted dc voltage output 32.4k? do not connect for current output core 10033-138 figure 38 . connections for current output showing voltage inversion single supply connections for single supply operation are shown in figure 39 and are similar to those for dual pow er supply when the device is ac - coupled. the analog inputs are all biased to half the supply voltage, but the output remains referred to groun d because the output of the ad8436 is a current source. an additional bypass connection is required at ignd to suppress ambient noise. ignd 4.7f rms 10f 0.47f vee cav vcc ognd 2 11 10 19 8 9 17 10m? 4 5 3 ibufout ibufin+ ibufin? out ad8436 4.7f 10033-039 figure 39 . connections for single supply operation recommended application figure 40 shows a circuit for a typical application for frequencies as low as power line, and above. the recommended averaging, crest factor and lpf capacitor values are 10 f, 0.1 f and 3.3 f. refer to the using the output b uffer section if additional low - pass filtering is required. ac in vcc vee dc out 10m vee cavg vcc obufout ignd obufin+ obufin? obufv+ out dnc ibufin? ibufout ibufin+ sum ibufv+ 1 4 3 2 5 8 7 6 9 12 11 10 16 15 14 13 10f 0.47f ognd ibufgn ccf 10f + 19 18 17 20 dnc rms 3.3f 0.1f ad8436 10033-040 figure 40 . typical application circuit converting to average rectified value to configure the ad8436 for rectified average instead of rms conversion, simply reduce the value of cavg to 470 pf (see figure 41 ). to enab le both modes of operation, insert a switch between capacitor cavg and pin cavg.
ad8436 data sheet rev. b | page 16 of 24 10033-200 ac in vcc vee dc out 10m vee cavg vcc obufout ignd obufin+ obufin? obufv+ out dnc ibufin? ibufout ibufin+ sum ibufv+ 1 4 3 2 5 8 7 6 9 12 11 10 16 15 14 13 10f 0.47f ognd ibufgn ccf 470pf cavg 10f + 19 18 17 20 dnc rms clpf 3.3f 0.1f ad8436 capacitor clpf, in conjunction with the internal 16k output resistor filters the rectified output, yielding the average-rectified value. capacitor cavg computes the mean in the implicit rms expression. for small values of cavg, the ac input waveform will still be fully rectified and appear at the output. disconnecting cavg defaults the computed result to average-value. a minimum of 470pf capacitance is required to maintain stability figure 41 . configuration for average rectified value
data sheet ad8436 rev. b | page 17 of 24 ad8436 evaluation board the ad8436 - evalz provides a platform to evaluate ad8436 performance. the board is fully assembled, tested , and ready to use after the power and signal sources are connected . figure 47 is a photograph of the board. si gnal connections are located on the primary and secondary sides, with power and ground on the inner layers . figure 42 to figure 46 illustrate the various design d etails of the board , including basic la yout and copper patterns. these figures are useful for reference for application designs. a word about u sing the ad8436 eval uation board the ad8436 - evalz offer s many options , without sacrificing simplicity. the board is tested and shipped with a 10 f averaging capacitor (c avg ) , 3.3 f low - pass filter capacitor (c8) and a 0.1 f (copt) capacitor to optimize crest factor p erformance. to evaluate minimum cost applications , remove c 8 and c opt. the functions of the five switches are listed in table 6 . tabl e 6 . switch function core_buffer selects core or input buffer for the input signal incoup selects ac or dc coupling to the core sdcout selects the output buffer or the core output at the dcout bnc. ibuf_vcc enable or disables the input buffer obuf_vcc enable or disables the output buffer all the i/o s are provided with test points for easy monitoring with test equipment. the input buffer gain default is unity; for 2 gain, install a 0603 0 resistor at p osition r5. for higher ibuf gains, remove the 0 resistor at p osition rfbh (there is an internal 10 k resistor from the obuf_out to ibufin?) and insta ll a smaller value resistor in p osition rfbl. a 100 resistor establish es a gain of 100. single supply operation requires re moval of resistor r6 and installing a 0.1 f capacitor in the same position f o r noise decoupl ing .
ad8436 data sheet rev. b | page 18 of 24 10033-142 figure 42 . assembly of the ad8436 - evalz 10033-143 figure 43 . ad8436 - evalz primary side copper 10033-144 figure 44 . ad8436 - evalz secondary side copper 10033-145 figure 45 . ad8436 - evalz power plane 10033-146 figure 46 . ad8436 - evalz ground plane
data sheet ad8436 rev. b | page 19 of 24 10033-147 figure 47 . photograph of the ad8436 - evalz 10033-148 tsum tacin vcc vee gnd5 gnd4 gnd3 gnd2 dc out tibufout tibfin+ vee cavg vcc obufout ignd obufin+ obufin? obufv+ out dnc ibufin? ibufout ibufin+ sum ibufv+ 1 4 3 2 5 8 7 6 9 12 11 10 16 15 14 13 tcavg core buf core buf tobfout gnd1 + tdcout gnd6 sdcout cin 10f dc ac trmsin tibfin? tognd tout tignd tobufin+ tobufin? tobufv+ tibufv+ en en dis ibuf_vcc dis tbufgn ognd buf gain ccf + vee + 19 18 17 20 incoup dnc rms tccf ad8436 + c1 3 10f 50v ?40c to +125c c6 1 2.2f c7 1 1.5f c3 3 0.1f cavg 10f ccf 0.1f x8r c4 0.1f clpf 3.3f c5 0.47f r3 1 8.06k r4 1 0 r8 0 r7 2 0 r6 3 0 r2 0 r5 4 0 r1 10m rfbl 5 dni rfbh 4 0 c2 10f 50v ?40c to +125c ?v 3 (grn) +v (red) obuf_vcc core_buf ac_in 1 optional components to configure ibufout as a filter. 2 remove r7 for core-only tests. 3 for single supply operation, remove r6, short or replace c3 with a 0 resistor and connect the supply ground or return to the green test loop ?v. 4 to configure the fet input buffer for gain of 2, install 0 resistor at r5 and remove rfbh. 5 rfbl is used to configure the input buffer for gain values >2. figure 48 . evaluation board schematic
ad8436 data sheet rev. b | page 20 of 24 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant t o jedec standards mo-220-wggd. 061609-b b o t t o m v i e w t o p v i e w e x p o s e d p a d pin 1 indica t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indica t or 2.65 2.50 sq 2.35 for proper connection of the expos ed pad, refer to the pin configuratio n and function descriptions section of this data sheet. 1 2 0 6 1 0 1 1 1 5 1 6 5 figure 49 . 20 - lead lead frame chip scale package [lfcsp_wq] 4 4 mm body, very very thin quad (cp - 20 - 10 ) dimensions shown in inches compliant t o jedec st andards mo-137-ad controlling dimensions are in inches; millimeter dimensions (in p arentheses) are rounded-off inch equiv alents for reference onl y and are not appropria te for use in design. 20 1 1 10 1 s e a t i n g p l a n e 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 4 ( 0 . 1 0 ) 0 . 0 1 2 ( 0 . 3 0 ) 0 . 0 0 8 ( 0 . 2 0 ) 0 . 0 2 5 ( 0 . 6 4 ) b s c 0 . 0 4 1 ( 1 . 0 4 ) r e f 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 6 ( 0 . 1 5 ) 0 . 0 5 0 ( 1 . 2 7 ) 0 . 0 1 6 ( 0 . 4 1 ) 0 . 0 2 0 ( 0 . 5 1 ) 0 . 0 1 0 ( 0 . 2 5 ) 8 0 coplanarity 0.004 (0.10) 0 . 0 6 5 ( 1 . 6 5 ) 0 . 0 4 9 ( 1 . 2 5 ) 0 . 0 6 9 ( 1 . 7 5 ) 0 . 0 5 3 ( 1 . 3 5 ) 0 . 3 4 5 ( 8 . 7 6 ) 0 . 3 4 1 ( 8 . 6 6 ) 0 . 3 3 7 ( 8 . 5 5 ) 0 . 1 5 8 ( 4 . 0 1 ) 0 . 1 5 4 ( 3 . 9 1 ) 0 . 1 5 0 ( 3 . 8 1 ) 0 . 2 4 4 ( 6 . 2 0 ) 0 . 2 3 6 ( 5 . 9 9 ) 0 . 2 2 8 ( 5 . 7 9 ) 08-19-2008-a figure 50 . 20 - lead shrink small outline package [ qsop ] (rq - 20) dimensions shown in inches and (millimeters)
data sheet ad8436 rev. b | page 21 of 24 ordering guide model 1 temperature range package description package option ad8436acpz -r7 ?40c to +125c 20- lead lead frame chip scale [lfcsp_wq] cp -20-10 ad8436acpz -rl ?40c to +125c 20- lead lead frame chip scale [lfcsp_wq] cp -20-10 ad8436acpz - wp ?40c to +125c 20- lead lead frame chip scale [lfcsp_wq] cp -20-10 ad8436 j cpz -r7 0 c to + 70c 20- lead lead frame chip scale [lfcsp_wq] cp -20-10 ad8436j cpz -rl 0 c to + 70c 20- lead lead frame chip scale [lfcsp_wq] cp -20-10 ad8436j cpz - wp 0 c to + 70c 20- lead lead frame chip scale [lfcsp_wq] cp -20-10 ad8436arqz - r7 ?40c to +125c 20- lead qsop [rq_20] rq -20 ad8436arq z - rl ?40c to +125c 20- lead qsop [rq_20] rq -20 ad8436arq z ?40c to +125c 20- lead qsop [rq_20] rq -20 ad8436b rqz -r7 ?40c to +125c 20- lead qsop [rq_20] rq -20 ad8436 b arqz -rl ?40c to +125c 20- lead qsop [rq_20] rq -20 ad8436 b rqz ?40c to +125c 20- lead qsop [rq_20] rq -20 ad8436 - evalz evaluation board 1 z = rohs compliant part.
ad8436 data sheet rev. b | page 22 of 24 notes
data sheet ad8436 rev. b | page 23 of 24 notes
ad8436 data sheet rev. b | page 24 of 24 notes ? 2011 C 2013 analog devices, inc. all rights reserved. trademarks and registe red trademarks are the property of their respective owners. d10033 - 0 - 1/13(b)

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